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Maxim MAX5865 Bedienungsanleitung Seite 5

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MAX5865
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈ 10pF on all digital outputs, f
CLK
= 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
= 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DAC ANALOG OUTPUT
Full-Scale Output Voltage V
FS
±400
mV
Output Common-Mode Range
1.29 1. 5
V
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC f
INI
= f
INQ
= 5.5MHz, DAC f
OUTI
=
f
OUTQ
= 2.2MHz, f
CLK
= 40MHz
75 dB
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
t
DOI
Figure 3 (Note 4) 7.4 9 ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid
t
DOQ
Figure 3 (Note 4) 6.9 9 ns
I-DAC Data to CLK Fall Setup
Time
t
DSI
Figure 4 (Note 4) 10 ns
Q-DAC Data to CLK Rise Setup
Time
t
DSQ
Figure 4 (Note 4) 10 ns
CLK Fall to I-DAC Data Hold Time
t
DHI
Figure 4 (Note 4) 0 ns
C LK Ri se to Q- D AC D ata H ol d Ti m e
t
DHQ
Figure 4 (Note 4) 0 ns
Clock Duty Cycle 50 %
CLK Duty-Cycle Variation
±15
%
Digital Output Rise/Fall Time 20% to 80% 2.6 ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
t
CSS
Figure 5 (Note 4) 10 ns
DIN to SCLK Setup Time t
DS
Figure 5 (Note 4) 10 ns
DIN to SCLK Hold Time t
DH
Figure 5 (Note 4) 0 ns
SCLK Pulse Width High t
CH
Figure 5 (Note 4) 25 ns
SCLK Pulse Width Low t
CL
Figure 5 (Note 4) 25 ns
SCLK Period t
CP
Figure 5 (Note 4) 50 ns
SCLK to CS Setup Time t
CS
Figure 5 (Note 4) 0 ns
CS High Pulse Width t
CSW
Figure 5 (Note 4) 80 ns
MODE RECOVERY TIMING CHARACTERISTICS
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
20
Shutdown Wake-Up Time
t
WAKE
SD
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error
40
µs
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