Maxim MAX5865 Bedienungsanleitung PDF herunterladen (Seite 15)

ADC System Timing Requirements

Figure 3 shows the relationship between the clock, ana-

log inputs, and the resulting output data. Channel IA

(CHI) and channel QA (CHQ) are simultaneously sam-

pled on the rising edge of the clock signal (CLK) and

the resulting data is multiplexed at the DA0–DA7 out-

puts. CHI data is updated on the rising edge and CHQ

data is updated on the falling edge of the CLK.

Including the delay through the output latch, the total

clock-cycle latency is 5 clock cycles for CHI and 5.5

clock cycles for CHQ.

Dual 10-Bit DAC

The 10-bit DACs are capable of operating with clock

speeds up to 40MHz. The DAC’s digital inputs,

DD0–DD9, are multiplexed on a single 10-bit bus. The

voltage reference determines the data converters’ full-

scale output voltages. See the Reference Configurations

section for setting reference voltage. The DACs utilize a

current-array technique with a 1mA (with 1.024V refer-

ence) full-scale output current driving a 400Ω internal

resistor resulting in a ±400mV full-scale differential out-

put voltage. The MAX5865 is designed for differential

output only and is not intended for single-ended appli-

cation. The analog outputs are biased at 1.4V common

mode and designed to drive a differential input stage

with input impedance ≥70kΩ. This simplifies the analog

interface between RF quadrature upconverters and the

MAX5865. RF upconverters require a 1.3V to 1.5V com-

mon-mode bias. The internal DC common-mode bias

eliminates discrete level setting resistors and code-gen-

erated level-shifting while preserving the full dynamic

range of each transmit DAC. Table 2 shows the output

voltage vs. input code.

MAX5865

Ultra-Low-Power, High-Dynamic-

Performance, 40Msps Analog Front End

______________________________________________________________________________________ 15

Figure 2. ADC Transfer Function

INPUT VOLTAGE (LSB)

-1-126 -125

256

2 x V

REF

1 LSB =

REF

= V

REFP

- V

REFN

REF

0+1-127 +126 +128+127-128 +125

(COM)

OFFSET BINARY OUTPUT CODE (LSB)

0000 0000

0000 0001

0000 0010

0000 0011

1111 1111

1111 1110

1111 1101

0111 1111

1000 0000

1000 0001

Figure 3. ADC System Timing Diagram

DOQ

DOI

5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)

DA0–DA7

D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q

CHI

CHQ

CLK

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 25 26

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