Q4. Why do the DS21372/DS2172 receive synchronizers sometimes lock to patterns other than
the transmitted pattern in repetitive-pattern mode?
A4. When the DS21372 and DS2172 are used to generate repetitive patterns, the receiver only searches for a repeating
pattern of the same length as the pattern being transmitted. It does not verify that the receive pattern exactly matches
the transmit pattern. Once the device has received a pattern of equal length, synchronization is declared. The device will
then count any deviations in the received pattern as bit errors. A received pattern of all zeros or all ones will cause the
device to synchronize no matter which pattern length is being transmitted. Also, any receive pattern length that is an
even divisor of the transmit pattern length will cause the device to synchronize. Consider the following examples that
meet the criteria above.
Transmit pattern 10111000 Original pattern programmed into device
Receive pattern 10111000 Device synchronizes to correct pattern
Receive pattern 00000000 Device synchronizes to wrong pattern
Receive pattern 11110000 Device synchronizes to wrong pattern
Receive pattern 10101010 Device synchronizes to wrong pattern
After synchronization is established, the software should check the pattern-receive registers to verify that the correct
pattern is being received. Also, the receive-all-zeros and receive-all-ones indicators show that the status register can be
used for pattern verification.
Q5. Why does the DS2174 design kit (DS2174DK) have neither a crystal nor an oscillator?
A5. Because we do not know the customer's working frequency domain, no crystal or oscillator is included in the
DS2174DK.
The DS2174DK does have an on-board selectable oscillator and an on-board selectable analog input for TCLK. The
customer can use either a signal generator or an appropriate oscillator for TCLK.
6. HDLC Questions
Q1. What are the differences between bridge and configuration mode in the HDLC controller?
A1. Configuration mode allows only the local bus to control and monitor the chip while the HDLC packet data is
transferred through the PCI bus. Data cannot be passed from the local bus to the PCI bus in this mode.
Bridge mode allows the host on the PCI bus to access the local bus. The PCI bus is used to control and monitor the chip
and transfer the packet data. Data can be mapped from the PCI bus to the local bus.
Q2. Does the DS31256 HDLC controller support 8-bit local bus mode?
A2. Yes, the 8-bit local bus is available in bridge mode and has two distinct PCI functions.
Function 0 Allows read and write operations to the DS31256 registers through the PCI bus using 8- or 16-bit wide
access. However, this function does not allow access to the DS31256 registers, which perform read and write operations
on the local bus.
Function 1 Allows read and write operations from the PCI bus to the local bus. The software must configure the LBW bit
in the LBBMC register to define the width of the local bus as 8 or 16 bits wide.
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