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DS33Z41DK

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ADDRESS MAP (ALL CARDS)

Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning

of the daughter card address space (shown previously).

Table 3. Overview of Daughter Card Address Map

OFFSET DEVICE DESCRIPTION

0X0000 to

0X0087

FPGA Processor board identification

0X1000 to

0X1FFF

DS33Z41 DS33Z41. Uses CS_X1.

0X2000 to

0X2FFF

DS21458 T1/E1 DS21458 resource card. Uses CS_X2.

0X4000 to

0X4010

FPGA

FPGA on DS21458 resource card. Used to facilitate IBO mode.

Default configuration of FPGA is compatible with non-IBO mode

functionality. The FPGA settings will require modification for use

with the DS33Z41 when device drivers are disabled.

Registers in the DS33Z41 and DS21458 can be easily modified using the ChipView host-based user-interface

software with the definition files previously mentioned.

Quad T1/E1 Resource Card FPGA Register Map

Table 4. Quad T1/E1 Processor Card FPGA Register Map

OFFSET

NAME

TYPE DESCRIPTION

0X4000 Rev Read only FPGA Rev

0X4001 delay_line1 Control Line 1 number of frame delay

0X4002 delay_line2 Control Line 2 number of frame delay

0X4003 delay_line3 Control Line 3 number of frame delay

0X4004 delay_line4 Control Line 4 number of frame delay

0X4005 MO+CLK Control Mode and clock ctrl

0X4006 UNUSED Control Unused / test

0X4007 UNUSED Control Unused / test

ID REGISTERS

REV: FPGA REV (Offset=0X4000)

FPGA Rev is read only, showing the current FPGA revision

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