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DS33Z41 Quad IMUX Ethernet Mapper
2 of 167
TABLE OF CONTENTS
1 DESCRIPTION....................................................................................................................7
2 FEATURE HIGHLIGHTS ....................................................................................................8
2.1 GENERAL ......................................................................................................................................8
2.2 LINK AGGREGATION (INVERSE MULTIPLEXING) ...............................................................................8
2.3 HDLC ........................................................................................................................................... 8
2.4 COMMITTED INFORMATION RATE (CIR) CONTROLLER.....................................................................8
2.5 X.86 SUPPORT..............................................................................................................................8
2.6 SDRAM INTERFACE ......................................................................................................................9
2.7 MAC INTERFACE ...........................................................................................................................9
2.8 MICROPROCESSOR INTERFACE ......................................................................................................9
2.9 TEST AND DIAGNOSTICS ................................................................................................................9
2.10 SPECIFICATIONS COMPLIANCE .....................................................................................................10
3 APPLICATIONS................................................................................................................11
4 ACRONYMS AND GLOSSARY........................................................................................12
5 MAJOR OPERATING MODES .........................................................................................13
6 BLOCK DIAGRAMS .........................................................................................................13
7 PIN DESCRIPTIONS.........................................................................................................14
7.1 PIN FUNCTIONAL DESCRIPTION ....................................................................................................14
8 FUNCTIONAL DESCRIPTION..........................................................................................22
8.1 PROCESSOR INTERFACE ..............................................................................................................23
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................23
8.1.2 Clear on Read.....................................................................................................................................23
8.1.3 Interrupt and Pin Modes......................................................................................................................23
8.2 CLOCK STRUCTURE ..................................................................................................................... 24
8.2.1 Serial Interface Clock Modes..............................................................................................................26
8.2.2 Ethernet Interface Clock Modes .........................................................................................................26
8.3 RESETS AND LOW-POWER MODES...............................................................................................27
8.4 INITIALIZATION AND CONFIGURATION ............................................................................................28
8.5 GLOBAL RESOURCES...................................................................................................................28
8.6 PER-PORT RESOURCES...............................................................................................................28
8.7 DEVICE INTERRUPTS....................................................................................................................29
8.8 SERIAL INTERFACE ......................................................................................................................31
8.9 LINK AGGREGATION (IMUX).........................................................................................................31
8.9.1 Microprocessor Requirements............................................................................................................33
8.9.2 IMUX Command Protocol ...................................................................................................................34
8.9.3 Out of Frame (OOF) Monitoring..........................................................................................................36
8.9.4 Data Transfer ......................................................................................................................................36
8.10 CONNECTIONS AND QUEUES........................................................................................................37
8.11 ARBITER ..................................................................................................................................... 38
8.12 FLOW CONTROL ..........................................................................................................................39
8.12.1 Full-Duplex Flow Control.....................................................................................................................40
8.12.2 Half-Duplex Flow control.....................................................................................................................41
8.12.3 Host-Managed Flow control ................................................................................................................41
8.13 ETHERNET INTERFACE PORT .......................................................................................................42
8.13.1 DTE and DCE Mode ...........................................................................................................................43
- DS33Z41 1
- Quad IMUX Ethernet Mapper 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1 DESCRIPTION 7
- 2 FEATURE HIGHLIGHTS 8
- 2.6 SDRAM Interface 9
- 2.7 MAC Interface 9
- 2.9 Test and Diagnostics 9
- 3 APPLICATIONS 11
- 4 ACRONYMS AND GLOSSARY 12
- 5 MAJOR OPERATING MODES 13
- 6 BLOCK DIAGRAMS 13
- 7 PIN DESCRIPTIONS 14
- 8 FUNCTIONAL DESCRIPTION 22
- 8.1 Processor Interface 23
- 8.2 Clock Structure 24
- Table 8-2. Reset Functions 27
- 8.5 Global Resources 28
- 8.6 Per-Port Resources 28
- 8.7 Device Interrupts 29
- 8.8 Serial Interface 31
- 8.9 Link Aggregation (IMUX) 31
- Sequence 01 32
- Sequence 02 32
- 8.9.2 IMUX Command Protocol 34
- 8.9.4 Data Transfer 36
- 8.10 Connections and Queues 37
- 8.11 Arbiter 38
- 8.12 Flow Control 39
- 8.13.1 DTE and DCE Mode 43
- 8.14 Ethernet MAC 46
- Figure 8-10. RMII Interface 47
- 8.15 BERT 48
- LoadVerify 49
- MatchVerify 50
- 802.3 MAC Frame 55
- Rate Adaption 55
- 9 DEVICE REGISTERS 60
- 9.1 Register Bit Maps 61
- 9.1.3 BERT Register Bit Map 62
- LI.TRX86SAPI 63
- LI.TRX86SAPIL 63
- TQOVFLS 64
- 9.1.6 MAC Register Bit Map 66
- 9.3 Arbiter Registers 81
- 9.4 BERT Registers 82
- 9.5.4 X.86 Registers 97
- 9.6.2 MAC Registers 124
- 10 FUNCTIONAL TIMING 140
- RXD[3:0] 141
- P R E A E M B L E 141
- 11 OPERATING PARAMETERS 142
- TXD[3:0] 144
- TXD[1:0] 146
- RXD[1:0] 147
- 11.7 SDRAM Timing 151
- LINK 4, CHANNEL 32 153
- LINK 1, CHANNEL 1 153
- LINK 2, CHANNEL 1 153
- Address Valid 156
- Data Valid 156
- 12 JTAG INFORMATION 159
- Capture-IR 161
- 12.2 Instruction Register 162
- 12.3 JTAG ID Codes 164
- 12.4 Test Registers 164
- 12.5 JTAG Functional Timing 165
- 13 PACKAGE INFORMATION 166
- 14 DOCUMENT REVISION HISTORY 167
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